Morgan Stanley’s Asia semiconductor team recently released a blockbuster research report, and analyst Charlie Chan’s view is straightforward: Google’s TPU capacity expansion is no longer just a “plan”—it’s a “fait accompli.”
Here’s the data—TPU shipments are expected to hit 5 million units by 2027, and ramp up to 7 million in 2028. That’s 12 million units in just these two years, directly surpassing the combined total of 7.9 million units over the past four years. With such aggressive capacity growth, the market is sensing a shift: Google may be turning TPUs from an “internal tool” into a “commercial product for external sale.”
If this really happens, how big is the potential? Morgan Stanley did the math: assuming 500,000 TPUs are sold annually, by 2027 Google could see $13 billion in revenue, directly adding $0.4 to earnings per share. What does this shift mean? Google is moving from being a “buyer” of AI chips to a “seller,” jumping right into the competition.
Many will say a single TPU can’t match the performance of a top-tier GPU. True, but Google is playing a different game—massive-scale cluster deployment plus cost-effectiveness, aiming to break Nvidia’s pricing dominance. The real battleground isn’t peak compute power; it’s the ecosystem and business model. Nvidia has developers locked in with CUDA, while Google is building its own ecosystem with TPUs and Gemini. When it comes to versatility and ecosystem maturity, Nvidia is indeed ahead, but as soon as top-tier clients start testing out TPUs, any cracks will be magnified by the capital markets.
Let’s mention some technical details for two related A-share listed companies:
**SMEE (Sai Microelectronics)** — A MEMS chip foundry with technical barriers in 8-inch MEMS wafer manufacturing. They use deep silicon etching to create micromirror structures, atomic layer deposition to control film stress, and wafer-level bonding for vacuum packaging ( to prevent air damping from affecting micromirror response speed and lifespan ). High gross margins directly reflect the process barriers.
**Dacolite** — Uses optical waveguide solutions to replace MEMS, possibly based on PLC or silicon photonics technology. Waveguides are etched onto the chip, and thermal-optic/electro-optic effects are used to change the refractive index for optical path switching. With no mechanical parts, switching speeds ( are at the microsecond or even nanosecond level ) and reliability far surpasses MEMS, but challenges remain in integration, insertion loss, and crosstalk control.
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NFTHoarder
· 10h ago
Damn, look at these numbers. If Google really starts selling TPUs, Jensen’s rice bowl is done for.
Honestly, this logic makes sense. It's not just about stacking performance, but about killing it with ecosystem + cost... How much do you guys think they’ll have to invest this round?
DecoLite's optical waveguide tech is really impressive. Eliminating mechanical components and getting response times down to the nanosecond level? That’s something... Not sure how their integration is going right now, though.
If this move actually manages to shake the CUDA ecosystem, I’ll believe it. For now, I’m just watching.
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SerLiquidated
· 10h ago
Damn, is Google really going to sell chips? Nvidia should be worried now.
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HashRateHermit
· 10h ago
Google's move towards independent chip development is truly impressive, but Huang's CUDA ecosystem moat is still solid... It all depends on whether top clients are willing to take the leap.
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GasGrillMaster
· 10h ago
Damn, TPU is so powerful! Google is really going head-to-head with Nvidia... But the weak ecosystem is definitely a serious drawback.
Morgan Stanley’s Asia semiconductor team recently released a blockbuster research report, and analyst Charlie Chan’s view is straightforward: Google’s TPU capacity expansion is no longer just a “plan”—it’s a “fait accompli.”
Here’s the data—TPU shipments are expected to hit 5 million units by 2027, and ramp up to 7 million in 2028. That’s 12 million units in just these two years, directly surpassing the combined total of 7.9 million units over the past four years. With such aggressive capacity growth, the market is sensing a shift: Google may be turning TPUs from an “internal tool” into a “commercial product for external sale.”
If this really happens, how big is the potential? Morgan Stanley did the math: assuming 500,000 TPUs are sold annually, by 2027 Google could see $13 billion in revenue, directly adding $0.4 to earnings per share. What does this shift mean? Google is moving from being a “buyer” of AI chips to a “seller,” jumping right into the competition.
Many will say a single TPU can’t match the performance of a top-tier GPU. True, but Google is playing a different game—massive-scale cluster deployment plus cost-effectiveness, aiming to break Nvidia’s pricing dominance. The real battleground isn’t peak compute power; it’s the ecosystem and business model. Nvidia has developers locked in with CUDA, while Google is building its own ecosystem with TPUs and Gemini. When it comes to versatility and ecosystem maturity, Nvidia is indeed ahead, but as soon as top-tier clients start testing out TPUs, any cracks will be magnified by the capital markets.
Let’s mention some technical details for two related A-share listed companies:
**SMEE (Sai Microelectronics)** — A MEMS chip foundry with technical barriers in 8-inch MEMS wafer manufacturing. They use deep silicon etching to create micromirror structures, atomic layer deposition to control film stress, and wafer-level bonding for vacuum packaging ( to prevent air damping from affecting micromirror response speed and lifespan ). High gross margins directly reflect the process barriers.
**Dacolite** — Uses optical waveguide solutions to replace MEMS, possibly based on PLC or silicon photonics technology. Waveguides are etched onto the chip, and thermal-optic/electro-optic effects are used to change the refractive index for optical path switching. With no mechanical parts, switching speeds ( are at the microsecond or even nanosecond level ) and reliability far surpasses MEMS, but challenges remain in integration, insertion loss, and crosstalk control.